The present invention relates to integrated circuits and, more particularly to, test structures and methods for on-wafer inspection of integrated circuits and other microelectronic devices.
Integrated circuits (ICs) comprise an arrangement of basic passive and active circuit elements, such as transistors, resistors and capacitors that are fabricated on a substrate or wafer. ICs are fabricated by a process of successively depositing layers of semi-conductive, conductive or insulating materials on the wafer and selectively etching portions of the deposited material. Deposition of a semi-conductor, conductor or insulator is followed by deposition of a layer of photosensitive material. The photosensitive material is exposed to light, through a precisely aligned mask, causing portions of the material to be chemically altered. Portions of the exposed photosensitive material are removed producing a photoresist layer with a pattern corresponding to the mask. A chemical etchant, applied to the surface, selectively removes the underlying semi-conductive, conductive or insulating layer except in those areas which are protected by the remaining photoresist. The remaining portions of the semi-conductor, conductor or insulator comprise a layer of one or more of the stratified, passive or active circuit elements. The photoresist layer is removed from the exposed surface of the wafer and the process is repeated until all of the strata of the circuit's elements have been laid down.
Referring to FIG. 1, typically, a plurality of dies 22, each comprising one or more integrated circuits, are formed on the surface of a wafer or substrate 20. Following fabrication, the individual dies are separated or singulated, typically by sawing the wafer along scribe or saw streets (indicated by a bracket) 24 between the dies. Each die containing a marketable integrated circuit is encased in a package and electrical connections are provided between the exterior of the package and the integrated circuit on the enclosed die. The. separation and packaging of a die comprises a significant portion of the cost of manufacturing an integrated circuit device. To monitor and control the fabrication process and avoid the cost of packaging defective dies, manufacturers commonly add electrical circuits or test structures 26 to the wafer that enable on-wafer inspection before the dies are singulated.
A wafer typically includes a plurality of test structures 26 that are distributed about the surface of the wafer enabling a portion of the wafer containing a defect to be isolated and identified by the testing. Referring to FIG. 2, a test structure 40 typically comprises a device under test (DUT) 42, a plurality of bond or probe pads 44 and a plurality of vias 46 connecting the probe pads on the surface of the substrate 20 to the circuit elements of the DUT which are typically fabricated beneath the surface. A DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the marketable integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor. The circuit elements of the DUT are typically produced with the same process and in the same layers of the wafer as corresponding elements of the marketable ICs. The marketable ICs are typically characterized “on-wafer” by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the integrated circuit, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the marketable ICs.
Many integrated circuits utilize single ended or ground referenced signaling that is referenced a ground plane, typically, at the lower surface of the substrate on which the active and passive devices of the circuit are fabricated. As a result of the physical make up of the devices of an integrated circuit, parasitic interconnections exist between many of the parts of the individual devices and between parts of the devices and the wafer on which the devices are fabricated. These interconnections are commonly capacitive and/or inductive in nature and have frequency dependent impedances. For example, the terminals of transistors fabricated on semi-conductive substrates or wafers are typically capacitively interconnected, through the substrate, to the ground plane. The impedance of this parasitic capacitive interconnection is frequency dependent and at higher frequencies the ground potential and the true nature of ground referenced signals becomes uncertain.
Balanced or differential devices utilizing differential signals are more tolerant to poor radio frequency (RF) grounding than single ended devices making them attractive for high performance ICs. A differential gain cell 50 is a balanced device comprising two nominally identical circuit halves 50A, 50B. When the transistors 52 of the differential gain cell are biased with a dc voltage, for example from a current source 54, and stimulated with a differential mode signal, comprising even (Si+1) and odd (Si−1) mode components of equal amplitude and opposite phase, a virtual ground is established at the symmetrical axis 56 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal. The quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended signals. In addition, the two waveforms of the differential output signal (So+1 and So−1) are mutual references providing faster and more certain transitioning from one binary value to the other for digital devices and enabling operation with a reduced voltage swing for the signal. Moreover, balanced or differential circuits have good immunity to noise, including noise at even-harmonic frequencies, because noise from external sources, such as adjacent conductors, tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode and signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics. Improved tolerance to poor RF grounding, increased resistance to noise and reduced power consumption make differential devices attractive for ICs that operate at higher frequencies. A differential gain cell is a common elemental device of differential or balanced circuits and a test structure comprising a differential gain cell enables on wafer testing and characterization of differential devices included in marketable ICs fabricated on the wafer.
As illustrated in FIG. 1, test structures are often fabricated on areas of the wafer that could otherwise be occupied by one or more dies containing the marketable integrated circuits. However, manufacturers face continuous pressure to reduce the cost of IC devices by increasing the number of dies fabricated on a wafer. Since the test structures serve no purpose after the dies are singulated, manufacturers have sought to locate the test structures in the saw streets between dies and, at the same time, to reduce the width of the saw streets to maximize utilization of the substrate's surface area.
While a DUT is usually small, the size of the test structure is typically determined by the area occupied by the probe pads. Test structures incorporating balanced devices typically require large areas of the wafer's surface because five probe pads 80, 82, 84, 86, 88 are required to sink and source the four differential signal components and bias the device. Two probes 60, 62 are required to facilitate simultaneous engagement of five probe pads with five probe tips 70, 72, 74, 76, 78. The probe pads of a differential test structure are typically arranged around the perimeter of the area in which the DUT is fabricated enabling a probe to be positioned on either side of the test structure. The size and separation of the individual probe pads are dictated by the need to co-locate the probe pads and the probe tips during testing and avoid interference between the adjacent conductors. Likewise, facilitating engagement of the probe pads with two probes and avoiding crosstalk between the two closely located probes dictates the separation between the rows of probe pads on either side of the test structure. However, locating two sets of interconnected probe pads in a saw street for simultaneous engagement by two probes that are relatively large compared to the features on the wafer has proven to be difficult.
What is desired, therefore, is a test structure including a DUT useful for testing integrated circuits comprising differential or balanced devices which can be fabricated in the saw streets between dies on a wafer or substrate.